The present invention relates to the field of semiconductor processing and, more particularly, to reduction of electromigration voids in metal interconnect structures.
The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing submicron-sized, low resistance-capacitance (RC) metallization patterns. This is particularly applicable when the submicron features, such as vias, contact areas, lines, trenches, and other shaped openings or recesses have high aspect ratios (depth-to-width) due to miniaturization. Conventional semiconductor devices typically comprise a semiconductor substrate, usually a doped monocrystalline silicon (Si), and plurality of sequentially formed interlayer dielectrics and electrically conductive patterns. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by inter-wiring spacings. Typically, the conductive patterns of vertically spaced metallization layers are electrically connected by vertically oriented conductive plugs filling via holes formed in the interlayer dielectric layer separating the metallization layers, while other conductive plugs filling contact holes establish electrical contact with active device regions, such as a source/drain region of a transistor, formed in or on a semiconductor substrate. Conductive lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type according to current technology may comprise five or more levels of metallization to satisfy device geometry and micro-miniaturization requirements.
A commonly employed method for forming conductive plugs for electrically interconnecting vertically spaced metallization layers is known as xe2x80x9cdamascenexe2x80x9d -type processing. Generally, this processing involves forming an opening (or via) in the dielectric interlayer, which will subsequently separate the vertically. spaced metallization layers. The via is typically formed using conventional lithographic and etching techniques. After the via is formed, the via is filled with conductive material, such as tungsten or copper, using conventional techniques. Excess conductive material on the surface of the dielectric interlayer is then typically removed by chemical mechanical planarization (CMP).
High performance microprocessor applications require rapid speed of semiconductor circuitry, and the integrated circuit speed varies inversely with resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As integration density increases and feature size decreases, in accordance with submicron design rules, the rejection rate due to integrated circuit speed delays significantly reduces manufacturing throughput and increases manufacturing costs.
One way to increase the circuit speed is to reduce the resistance of a conductive pattern. Aluminum is conventionally employed because it is relatively inexpensive, exhibits low resistivity, and is relatively easy to etch. However, as the size for openings for vias/contacts and trenches is scaled down to the submicron ranges, step coverage problems result from the use of aluminum. Poor step coverage causes high current density and enhanced electromigration. Moreover, low dielectric constant polyamide material, when employed as dielectric interlayers, create moisture/bias reliability problems when in contact with aluminum, and these problems have decreased the reliability of interconnections formed between various metallization layers.
Copper (Cu) and Cu-based alloys are particularly attractive for use in VLSI and ULSI semiconductor devices, which require multi-level metallization layers. Copper and copper-based alloy metallization systems have very low resistivities, which are significantly lower that tungsten and even lower than those of previously preferred systems utilizing aluminum and its alloys. Additionally, copper has a higher resistance to electromigration. Furthermore, copper and its alloys enjoy a considerable cost advantage over a number of other conductive materials, notably silver and gold. Also, in contrast to aluminum and refractory-type metals, copper and its alloys can be readily deposited at low temperatures formed by well-known (wet) plating techniques, such as electroless and electroplating techniques, at deposition rates fully compatible with requirements of manufacturing throughput.
FIG. 1 depicts a schematic cross-section of a portion of a metal interconnect structure employing copper damascene technology. The lower level metal layer 10 (including a copper line), also referred to as M1, is connected to a higher level metal layer 16 (including a copper line) through a via 14. Barrier layers 18 and 20, formed of nitride, for example, cover the metal layers 10, 16. The metal layer 10, 16 are separated by a dielectric layer 12, such as formed by an oxide, for example. The via 14 is filled with metal to form a conductive plug 15.
The formation of the via 14 involves performing a via etch through the dielectric layer 12 and the barrier layer 20, stopping on the underlying metal layer 10. A pre-sputter etch process, using argon, for example, is normally employed prior to the via barrier and copper deposition.
Electromigration (EM) has been defined as the transport of metal atoms by momentum exchange between electrons, moving under the influence of a field, and metal ions. Two of the critical interfaces for electromigration in the copper damascene structure of FIG. 1 are the interface V1M1 at 22 and V1M2 at 24. Electromigration testing of the V1M1 interface 22 involves flowing electrons from the upper copper line in metal layer 16 (M2) through the conductive plug 15 and the via 14 and into the lower copper line in metal layer 10 (M1). Electromigration testing of the V1M2 interface 24 involves electrons flowing in the opposite direction. In the case of the V1M1 interface 22, electromigration voids typically generate at the copper/nitride or (copper/barrier) interface at the via 14. This is depicted in FIG. 2, where the electromigration void 26 is shown. The presence of a electromigration void 26 reduces the reliability of the device.
When aluminum is used as the interconnect material, it is well known that many alloying elements may be employed to improve the aluminum resistance to electromigration. One of the most widely used alloying elements is copper in aluminum. When copper is added in small concentrations to aluminum, the electromigration reliability increases by orders of magnitude. Similarly, alloying elements for copper have been under study. However, there are process differences between aluminum and copper that render the insertion of an alloy in the copper process flow a challenging proposition. For example, aluminum is a deposition, pattern and etch process, while copper is typically a damascene process with a physical vapor deposition (PVD) seed and electrochemical fill process.
Attempts have been made to introduce the alloy into the copper lines during electrochemical deposition, but many alloys of copper are not electrically active in aqueous solution. Another potential solution is to sputter the copper alloys during the PVD copper seed deposition, but there is a problem in that the alloying elements tend to sputter at a different rate than the copper matrix since different metals have different sputter yields. Another problem has been alloying element uniformity in the line after processing, which is determined by the seed thickness, aspect ratio, percent alloy in the copper target, annealing conditions, and plating process. An additional problem affecting alloy uniformity is linewidth variations.
There is a need to provide a metal interconnect structure and method of making the same that employs copper in the metallization layers and improves electromigration properties at critical electromigration failure sites.
These and other needs are met by embodiments of the present invention which provide a metal interconnect structure comprising a copper line and a dielectric layer over the copper line. The via extends through the dielectric layer to the copper line. The copper alloying element layer, comprising a copper alloying element, lines the via and covers the copper line exposed by the via. A conductive plug fills the via. A solid solution of copper and the alloying elements is provided in the copper line only in the area of the copper line adjacent to the conductive plug.
By providing a copper alloying element layer that lines the via that is directly over the copper line, a solid solution of copper and the alloying element may be formed in the area of the copper line directly underneath the conductive plug. Hence, the solid solution of copper and the alloying element is provided at the most critical electromigration failure site, i.e., the fast diffusion site below the via in the underlying copper line.
The earlier stated needs are also met by another aspect of the present invention which provides a method of selectively alloying an element to interconnect metallization. This method comprises the steps of etching an opening through a dielectric layer to expose a portion of an underlying metallization layer and form a via. An alloying element layer is deposited within the via to line the via and cover the exposed portion of the metallization layer. A solid solution of the alloying element and the metallization layer are formed at the exposed portion.
Still further aspects of the present invention provide a method of providing an alloying element for copper below a via at a top of a copper line covered by a dielectric layer. This method deposits a layer of an alloying element within a via to line the via and cover the top of the copper line that is exposed by the via. A conductive plug is formed in the via and annealing is performed. The annealing causes formation of a solid solution of the alloying elements at the top of the copper line that is covered by the layer of the alloying elements.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.